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    Tommi_Wei的博客:UVM Register Model set() and write()

    作者:[db:作者] 时间:2021-09-09 13:39

    在这里插入图片描述

    In our register model, we have mirror value and desired value.
    Due to our register’s value will change easily, we need to create an variable keep up with DUT, it called mirror value.

    If we want to write 1 to this register, we could use write(‘h1), mirror value and desired value are both update.

    Another way, we could use set(‘h1), desired value ‘h1, but mirror value not change. So we need invoke update(),update() will check desired value and mirror value whether fit.

    If not fit, update() will write desired value to DUT, and update mirror value.

    As far as i am concerned, write() maybe more easy than set, but it seems not very professional!

    Author: Tommi Wei

    cs