Library Ieee;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Decl7s IS
PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LED7s:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END;
ARCHITECTURE one OF Decl7s IS
BEGIN
PROCESS(A)
BEGIN
CASE A IS
WHEN “0000” => LED7s <=“0111111”;
WHEN “0001” => LED7s <=“0000110”;
WHEN “0010” => LED7s <=“1011011”;
WHEN “0011” => LED7s <=“1001111”;
WHEN “0100” => LED7s <=“1100110”;
WHEN “0101” => LED7s <=“1101101”;
WHEN “0110” => LED7s <=“1111101”;
WHEN “0111” => LED7s <=“0000111”;
WHEN “1000” => LED7s <=“1111111”;
WHEN “1001” => LED7s <=“1101111”;
WHEN “1010” => LED7s <=“1110111”;
WHEN “1011” => LED7s <=“1111100”;
WHEN “1100” => LED7s <=“0111001”;
WHEN “1101” => LED7s <=“1011110”;
WHEN “1110” => LED7s <=“1111001”;
WHEN “1111” => LED7s <=“1110001”;
WHEN OTHERS => NULL;
END CASE ;
END PROCESS;
END;